嵌入式OS--4G手機操作系統

手機/網絡/動漫游戲開發

嵌入式OS--WinCE

單片機培訓

嵌入式硬件設計

電子電路設計

嵌入式OS--VxWorks

PowerPC嵌入式系統/編譯器優化

3G手機軟件測試、硬件測試

云計算、物聯網

開源操作系統Tiny OS開發

　

　

公益培訓通知與資料下載

曙海招聘啟示

　　培訓班新動態 　

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In this workshop, you will perform high-level design steps necessary to synthesize, analyze, and verify a multi-voltage design with shutdown requirements using the IEEE 1801 UPF-based Synopsys Eclypse Low-Power Flow. You will:

Identify the library requirements to implement a MV low-power design

Create, modify, interpret, and apply power-intent (UPF) files

Correctly specify PVT requirements for MV low-power optimizations

Perform low-power RTL synthesis using top-down and hierarchical UPF methodologies

Generate a gate level design that is MV-clean

Insert power-domain aware scan chains

Check for logic equivalence of RTL and gate-level designs

Conduct static timing analysis on the pre-layout design

Analyze average and peak power consumptions

Verify the results of running MV rule checks on the gate-level design

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At the end of this workshop, using the Front-End Synopsys Eclypse Low-Power Flow, you should be able to perform the following high-level design objectives:

Create, interpret, and apply UPF files that capture the stated power intent requirements

Synthesize designs for the power intent and power-optimization requirements using both top-down and hierarchical UPF methodologies

Describe the effect of performing a supply-net-aware always-on synthesis

Insert scan chains taking into account the existing power domains while minimizing switching activity

Ensure that the gate-level design is MV clean

Ensure equivalence checking of logic functionality between RTL and gate- level using the design and UPF files

Perform static timing analysis

Generate peak and average power analysis reports/waveforms

Analyze gate-level design for MV rule violations

Write out all needed files for physical implementation

Logic design and/or verification engineers who have a need to implement, analyze, and verify designs requiring the lowest possible power consumption using the Synopsys Front-End Eclypse Low Power Flow. CAD Engineers and Managers responsible for Low Power flow will also find this workshop beneficial.

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To benefit the most from the material presented in this workshop, students need:

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A basic working knowledge of Synopsys Design Compiler and PrimeTime tools. Working knowledge of the other Synopsys tools used (list at the end of course description) in the workshop is desirable, but not required, to complete this workshop

An awareness of the basics of low-power design techniques. This workshop teaches how to implement these techniques

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1.

Introduction to Low Power Solution

Specifying Power Intent: UPF (Lab)

RTL Synthesis (Lab)

Hierarchical UPF Flow and DFT (Lab)

2.

Lab-4: Hierarchical UPF Flow and DFT (Lab Contd.)

Logic Equivalence Checking (Lab)

Static Timing and Power Analysis (Lab)

Multi Voltage Rule Checking (Lab)?